1. Field of the Invention
The present invention relates to a power feed device to power pins of an electrical component, more particularly relates to a built-in capacitor type power feed device designed to feed power to various types of power pins of a ball gate array (BGA) or other electrical component from an on board power (OBP) or other power supply without going through patterns included in the printed circuit board by arranging a power bar and ground bar outside of the printed circuit board, providing a high dielectric layer between them, and going through the power bar and ground bar.
2. Description of the Related Art
In recent years, the reduction in the noise margin of the power supply system accompanying the lower drive voltages of electrical components such as BGAs and the noise between the power and ground accompanying simultaneous switching waveforms are becoming major problems.
FIG. 1A is a plan view, seen from below, of a BGA fed with power by a conventional power feed device. In the figure, 10 indicates a BGA at the back side of which power pins 1 to 6 are arranged at predetermined positions in the row direction and column direction by solder balls. Each power pin 1 is an electrode supplied with for example a 3.3V power voltage V1. Each power pin 2 is an electrode supplied with for example a 3.3V reference voltage V2. Each power pin 3 is an electrode supplied with for example a 3.3V auxiliary power voltage V3. Each power pin 4 is an electrode supplied with for example a 5V power voltage V4. Each power pin 5 is an electrode supplied with for example a 5V reference voltage V5. Each power pin 6 is an electrode supplied with for example a 5V auxiliary power voltage V6.
FIG. 1B is a cross-sectional view showing one example of a conventional power feed device. In the figure, 12 indicates a printed circuit board arranged below the BGA 10, 13 indicates an OBP arranged on the printed circuit board 12 and generating a 3.3V voltage, 14 indicates an OBP arranged on the printed circuit board 12 and generating a 5V voltage, 15 indicates a copper foil power layer included in the printed circuit board 12 and forming a 3.3V power layer, 16 indicates a copper foil power layer included in the printed circuit board 12 and forming a 5V power layer, 17 indicates a via passing through the printed circuit board 12 for supplying the OBP 13 output voltage 3.3V to the power layer 15, 18 indicates a via passing through the printed circuit board 12 for supplying the OBP 14 output voltage 5V to the power layer 16, and 19 to 24 are vias passing through the printed circuit board 12 corresponding to the power pins 1 to 6. The bottom of the BGA 10 is shown by a cross-section along the dot-chain line of FIG. 1A. The 3.3V power layer 15 is connected through the vias 19 to 21 to the power pins 1 to 3, while the 5V power layer 16 is connected through the vias 22 to 24 to the power pins 4 to 6.
Instead of preparing the reference voltage V2 inside the OBP 13, a voltage output from the other OBP 14 generating the 5V voltage is divided by a voltage division circuit (formed on the printed circuit board 12, but not shown) to prepare a 3.3V reference voltage V2.
The BGA 10 is actually supplied with a plurality of types of power voltage and signals. For this reason, the printed circuit board 12 includes, though not shown, a plurality of other power layers and signal patterns.
FIG. 2 shows one example of a circuit included in the BGA. In the figure, 22 indicates a driver and 24 a receiver. The BGA has inside it a driver circuit and a receiver circuit. The driver and the receiver are connected by connecting different BGAs. A single BGA never has the driver and receiver connected inside it. If considering this by FIG. 2, 22 and 24 show the case of a different BGA driver circuit and receiver circuit connected by patterns on a printed circuit board. The driver 22 is supplied with the 3.3V power voltage V1 and auxiliary power voltage V3, while the receiver 24 is supplied with the 3.3V power voltage V1. These power voltages are output from the OBP 13 and are supplied through the power layer 15 to the power pins 1 to 3.
FIG. 3 shows another example of a circuit included in the BGA. In the figure, 32 indicates a driver and 34 a receiver. The driver 32 is supplied with the 5V power voltage V4 and the auxiliary power voltage V6, while the receiver 34 is supplied with the 5V power voltage V5. These power voltages are output from the OBP 14 and supplied through the power layer 16 to the power pins 4 to 6.
The reference voltage V2 shown in FIG. 2 is used as the criteria for judgment as to if the output voltage of the driver 32 of the circuit shown in for example FIG. 3 is the high level or low level. For example, when the output voltage of the driver 32 is higher than 3.3V, it is judged that the voltage is the high level, while when it is 3.3V or less, it is judged as the low level.
For reference to this related art, see Japanese Patent Publication (A) No. 2-003957, Japanese Patent Publication (B) No. 7-120227, and Japanese Patent Publication (A) No. 6-223632.
In the case of a component like a BGA where a plurality of voltage power supplies are required, as shown in FIGS. 1A and 1B, the situation where the V1, V2, and V3 are the same voltages, but the applications differ frequently occurs in practice. In this example, the driver-receiver power voltage V1 of FIG. 2 is a voltage the same as the receiver reference voltage V2 of FIG. 3. Further, physically, for example when using a 1 mm pitch BGA, since the distances between pins is in the narrow region of 1 mm, the pins are easily affected by each other in structure.
In the circuit of FIG. 2, when a current I flows through the driver 22, a noise in accordance with that current, that is, Vn=LdI/dt, occurs at the power bar 15 and as a result the power layer 15 fluctuates in voltage and the reference voltage V2 fluctuates. This being the case, the reference voltage for judging if the output voltage of the driver 32 of the circuit shown in FIG. 3 is the high level or low level will fluctuate. For example, if the reference voltage V2 changes to 3.5V and the output voltage of the driver 32 is 3.4V, while originally speaking the output of the driver 32 should be the high level, the change of this reference voltage causes it to be misjudged as the low level. Further, depending on the component, the component may also contain pins requiring an analog system power supply (PLL: phase-locked loop). In general, an analog system power supply is sensitive to noise, so for example even if the same voltage as the digital system power supply, physical separation is necessary. This is also one example where the voltages are the same, but the applications differ, so separation would be better.
Further, there were the problem that a printed circuit board included a large number of power layers and signal layers and therefore the number of conductor layers provided in the printed circuit board was large and the dimensions became larger and the problem that if trying to make the printed circuit board smaller in thickness, the conductor layers became greater in mounting density and production became difficult. For example, when the BGA 10 is a 1152-pin field programmable gate array (FPGA), there are 3.3V Vccaux pins (eight pins), but specification-wise, these Vccaux pins have to be activated before all of the other power supplies (Vcc and Vref). For this reason, in the past, two separate layers, that is, a Vccaux power layer and a Vcco and Vref power layer, were necessary.